【Verilog】記述言語で論理設計 Project2【VHDL】

こんなんじゃだめかいのう。
library ieee;
use ieee.std_logic_1164.all;
package SystemLib is
    constant SystemNumber :   integer := 0    ;
    function TABLE_A return std_logic_vector;
end SystemLib;
package body SystemLib is
    function TABLE_A return std_logic_vector is
        variable var: std_logic_vector(3 downto 0);
    begin
        case (SystemNumber) is
            when 0      =>  var :=  "0011"  ;
            when others =>  var :=  "1010"  ;
        end case;
        return var;
    end;
end SystemLib;